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Add DWC2 cache maintenance routines for STM32 #2963

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Add DWC2 cache maintenance routines for STM32 #2963

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HiFiPhile
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@HiFiPhile HiFiPhile commented Jan 25, 2025 •
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Describe the PR

  • Support DMA + DCache ON
  • Refactored buffer alignment macro to take into account cache line size

Now #define CFG_TUD_DWC2_DMA_ENABLE 1 is enough.

** Need rebase after #2960

@HiFiPhile
Update deps.
6d1ed1e 
Signed-off-by: HiFiPhile <[email protected]>
@HiFiPhile
Add NUCLEO-H7S3L8 BSP.
f6f20e1 
Signed-off-by: HiFiPhile <[email protected]>
@HiFiPhile
Fix CI.
979d790 
Signed-off-by: HiFiPhile <[email protected]>
@HiFiPhile
Add STM32 DWC2 cache support.
8cf981e 
Signed-off-by: HiFiPhile <[email protected]>
@HiFiPhile
Enable DCache in BSP.
8ecfc15 
Signed-off-by: HiFiPhile <[email protected]>
@HiFiPhile
Align buffer to cache line size.
5995244 
Signed-off-by: HiFiPhile <[email protected]>
@HiFiPhile
Update examples & BSP.
1d984c2 
Signed-off-by: HiFiPhile <[email protected]>
@HiFiPhile HiFiPhile force-pushed the stm32_cache branch 2 times, most recently from 9022544 to 7b6b813 Compare January 25, 2025 13:11
@HiFiPhile
Fix CI.
adb3c80 
Signed-off-by: HiFiPhile <[email protected]>
@HiFiPhile HiFiPhile mentioned this pull request Jan 25, 2025
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Looks like my HIL instance has license issue, I think we can add the env locally.

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